Marvell(ÃÀÂúµç×ӿƼ¼¹«Ë¾)
Design Engineer
10K-20K ÉϺ£ Ó¦½ì±ÏÒµÉú ˶ʿ¼°ÒÔÉÏ È«Ö°
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Design Engineer
position description
Candidates will be
involved in the whole ASIC design flow from RTL coding through P&R support,
which includes logic design, DFT planning and implementation, logic synthesis,
power optimization, static timing analysis and sign-off. Candidates will also
work closely with analog design teams on IP integration, with P&R engineers
on chip floor planning and timing optimization, and with product/test engineers
on ATE tests.Job Description
Work closely with
frontend and backend design teams, as well as test engineers. Participate
in logic design for some timing critical blocks in SOHO switch/PHY chips and
ASICs. Perform logic synthesis, floor planning, timing analysis and
timing signoff for chip tapeout. Work on DFT designs including MBIST, EDT, OCC,
JTAG. Run Mentor and Synopsys tools to create and verify ATPG patterns. Work
with test engineers to build up and debug test programs.Job qualification
¡¤ MSEE degree
¡¤ 0~2 years of hand-on
experience in digital design, running EDA tools of simulation, synthesis,
timing analysis and formal verification
¡¤ Solid knowledge and
background in ASIC development
¡¤ Good communication
skills
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http://www.moore.ren/job/detail.htm?jobId=1200374&invitecode=89cb2278-4b99-4e34-8b22-784b997e3412