Digital / SoC Design Engineer (Senior)

Job description:
- This position is for a digital design engineer supporting mixed signal SoC developments.
- RTL coding for logic models.
- Simulation/verification of functionalities at both module level and top level.
- Module level synthesis / timing analysis / P&R.
- Design/verification and top-level function verification.
- Silicon debug of related model functionalities.

Qualifications:
- BSEE with minimum 3-year or MSEE with minimum 1-year experience of digital experience.
- Experience on serial interface design (eg. SPI, I2C).
- Relevant experience in high-speed digital design (Flow: custom layout + ASIC P&R flow) is a must.
- Solid knowledge of digital design building blocks.
- Strong skills of Verilog RTL coding, Place & Route, timing closure, verification and debug.
- Hands on experience in EDA tools such as Cadence NC-Sim, Synopsys DC, PT, etc.
- Desired: Closed-Loop Control Theory and Adaptation, Digital Filtering, Mixed-Mode Simulations such as Verilog-A.

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We are a Shanghai/SiliconValley based stealth-mode semiconductor startup, and backed by the world¡¯s leading venture capital firm for hardware. Our returnee founders are successful entrepreneurs with backgrounds from Stanford, Fudan, Intel, LSI, and nVidia. They have been collectively involved in six successful startups, with their last IC startup in Shanghai previously acquired for 200+ mil-RMB. 
Our company culture is like a Silicon-Valley style startup, with a unique USA/ Chinese-blend of lifestyle and innovation. Our vision is to learn, challenge, and grow together, creating exponential value for our customers, ourselves, and our company.

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